My Cpu

My own :)

Not so long ago, I found a link on usenet talking about a CPU made with relays (look at http://www.cs.pdx.edu/~harry/Relay/index.html).
I found the principle very cool, and now I want to do my own !
However, relays are very costy parts. They are heavy and juice hungry. So, why relays ? Because it's neat ! you can see your cpu working !

Well, you're hearing it too…
So, as the relays cost money, I'll try to make is so it requires the less relays possible. Of course, I'll have a working machine *in simulation* even before buying the hardware.

Doing a cpu isn't a task you're doing as fast as writing an hello world. You don't take your soldering iron and tell “now, which gate do I solder ?”
The first task is making the requirements. The requirement, as in every evolutary software, moves along with the customer's needs. So, this page will contain the most up to date specifications.

Here is a list of what I want Mycpu to be able to:

• Cheap. Thus, no fancy 32 bits bus and such.
• Fast. Yeah, I won't do a massparallel cracking device with relays. 1 expect a 1Hz clockrate.
• Able to do some real world computation. As a turing complete device, I'd like to be able to calculate a few digits of Pi or e.
• Be fun. That's all about it ! who's going to run a database server on a 1hz computer anyway ?
• Educative. This is why I'm documentating the whole from the start of the project.

I don't need a beast. I think a 8bits cpu is more than enough. Also, I feel that the Risc architecture is a must, because multiple-cycles cisc instruction are going to need more logic gates. Also, cisc instruction are very long. It's not very suited to my cpu.

• 3 registers : A,B and W. A and B are the “doors” with memory. You can only fetch from memory into A or B. Arithmetic operations take operands from A and B and put results into W. Also, W is the “Tests” registers in which comparaisons are done.
• 1 Status Bit : result of a comparaison, it says “Yes, skip instruction” or not.
• 8 bits data memory bus. Each word is 8 bits long, so there are in total 1024 bits of memory. I don't know yet if I'm going to make it with relays. I doubt.
• 8 bits Instruction bus. The instruction bus is separated from the data for simplicity (and efficienty), regarding the Harvard architecture. The size of the instruction bus may be changed without too many problems (no need to change the instruction len). A single instruction word is 11 bits long. So, code memory is 256*11bits word long. I'm going to use a rom, or hardcode code with wires.
• UAL will be able to do additions, substractions, left and right shifts, plus the basic logical functions (or, and, xor, not).

Looking at relays specifications, I see that the commutation time of a relay is more or less 5ms. That mean, a cycle will end when every relay has commuted. So, a cycle time is the sum of commutation times of all relays in a straight line. I'll calculate it exactly when the simulated implementation is done, but I don't believe I'll be able to make it work at more than 1 cycle by second.

Yeah, you heard it. 1 Hertz.

It might look trivial (it looked so for me) but designed an efficient binary executable format is not easy !
you have to make it simple so the instruction decoding unit is very simple and doesn't cost too much gates. Actually, I designed it using OpenOffice.org's Calc. One of the tricky part was the Tests :
There is a value in register W you want to test for different aspects : =0, !=0, <0, ⇐0, >=0, >0.
Thus, there are 3 input bits from the instruction opcode. The test unit only need two bits of information from W : the bit sign (bit 0) and the sum of all bits (to test zeroesness).
I found out which convention for the opcode use the less gates.
more information in assembler.pdf

Ever heard about the graph theory ? It says you can explain a week of procrastination by a well choosend graph :)
More seriously, this is the graph of the data flow. Of course it's not definitive, but it gives an idea of what each part of the cpu is doing. A later version will include more information on the arrows, because they don't tell *which* information is given. for instance, you may not guess that the arrow from instruction unit to Program code means “Instruction Address”. Another time maybe.

The first thing that needs to be tested is the instruction set constitency, as well as the practibility (can the cpu resolve problem and impress chicks ?)

Current version: onehertz-0.0.2.tar.gz

Includes:

• assembler
• disassembler
• simulator (virtual machine)

I'm not going to write my programs in binary in 2006. I'll make a lex/yacc based assembler, quick and dirty.

This virtual machine will emulate the cpu behaviour. Not its internals. So, it'll will receive a binary program as input and tell the result. Eventually, I'll be able to debug the programs and make some estimations about the time needed to run a program.
And i'll know if 256 instruction words are enough to calculate pi or e.

formule pour le calcul de pi : ça va être sportif !

Going a step forward, I'll make independant parts of a program that simulates the in and outs of the cpu. It's time to find a conceptual defect in my graph…

I'm probably going to use one of well known electronic drawer that makes a connection matrix. I'll make a program to simulate the relays, and I'll test each unit separatly, then together… And i'll know if it really works !
I found a cool little java app : http://www.tetzl.de/java_logic_simulator.html#demo It's not very “serious” but it's more than enough to draw the initial schematics

I'll take my soldering iron and put all that pieces together…